The present invention relates generally to semiconductor devices and the fabrication thereof and, more particularly, to a semiconductor device having a thin body region and a high-K gate dielectric.
A pervasive trend in modern integrated circuit manufacture is to produce semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs), that are as small as possible. In a typical MOSFET, a source and a drain are formed in an active region of a semiconductor layer by implanting N-type or P-type impurities in the layer of semiconductor material. Disposed between the source and the drain is a channel (or body) region. Disposed above the body region is a gate electrode. The gate electrode and the body are spaced apart by a gate dielectric layer. It is noted that MOSFETs can be formed in bulk format (for example, the active region being formed in a silicon substrate) or in a semiconductor-on-insulator (SOI) format (for example, in a silicon film that is disposed on an insulating layer that is, in turn, disposed on a silicon substrate).
Although the fabrication of smaller transistors allows more transistors to be placed on a single monolithic substrate for the formation of relatively large circuit systems in a relatively small die area, this downscaling can result in a number of performance degrading effects. For example, in SOI devices with a thin body (e.g., about 15 nm or less) it may become difficult to adequately control the thickness of the channel.
Accordingly, there exists a need in the art for semiconductor devices, such as MOSFETs, that have enhanced performance and that are made with relatively precise dimensions. There also exists a need for corresponding fabrication techniques to make those semiconductor devices.
According to one aspect of the invention, the invention is directed to a fully depleted semiconductor-on-insulator (SOI) field effect transistor (FET). The FET includes a layer of semiconductor material disposed over an insulating layer, the insulating layer disposed over a semiconductor substrate. A source and a drain are formed from the layer of semiconductor material. A body is formed from the layer of semiconductor material and disposed between the source and the drain. The layer of semiconductor material is etched such that a thickness of the body is less than a thickness of the source and the drain and such that a recess is formed in the layer of semiconductor material over the body. A gate is formed at least in part in the recess and the gate defining a channel in the body, the gate including a gate electrode spaced apart from the body by a gate dielectric made from a high-K material.
According to another aspect of the invention, the invention is directed to a method of forming a fully depleted semiconductor-on-insulator (SOI) field effect transistor (FET). The method includes providing a layer of semiconductor material, the layer of semiconductor material disposed over an insulating layer, and the insulating layer disposed over a semiconductor substrate; forming a dummy gate on the layer of semiconductor material; doping the layer of semiconductor material to form a source and a drain, and a body region between the source and the drain; removing at least a portion of the dummy gate; etching the layer of semiconductor material to form a recess therein, the recess formed in at least the body region of the layer of semiconductor material such that a thickness of the body is less than a thickness of the source and the drain; and forming a gate at least in part in the recess and the gate defining a channel in the body, the gate including a gate electrode spaced apart from the body by a gate dielectric made from a high-K material.